(Article published in 'Electronics For You' magazine in 1982 )
(and subsequently in 'Electronics Projects- Vol 3')
Gone are the
days when there used to be more peons in an office than the executives. A mere
call from an executive would make a whole army of peons rush to his service.
Nowadays, a number of executives in an office are attended to by a single
office boy. And naturally, the office boy is now a busy man, having to attend
to the needs of so many executives.
This office
call bell system has been designed keeping the above fact in mind. Its salient
features are:
- Only one bell is shared by all the executives.
- The system provides a visual indication of the caller.
- It automatically provides a reminder if the call remains unattended.
The circuit has been designed around readily
available TTL integrated circuits.
The circuit
The
circuit shown in Fig. 1 features four stations, though the number of stations
can be easily increased by adding similar modules. For each station, two nand gates of IC 7400 are wired as a R-S
flip-flop.
Pin 1 of IC1 is
connected to positive supply rail through resistor R5, and can be connected to
ground through bell- push switch SA. Since pin 1 of IC1 is normally at the
positive supply voltage, the input to the flip-flop is at logic 1. Logic 0
appears at the input as soon as switch SA is depressed. Similarly, reset input (to
pin 5) of the flip-flop (ICI) is normally held at logic 1, unless the master
reset switch SR is depressed—which provides logic 0 at pin 5 of ICI. Likewise, set and
reset inputs of the other flip-flops are normally held at logic 1, but change
to logic 0 when their respective bell- push switches or the master reset switch
is depressed.
Further,
the set inputs of the different flip-flops are wired as inputs of quad-input nand
gate IC3 (a). Since all these inputs are normally held at logic 1, the output
of this gate is at logic 0. However, if any of the bell-push switches is
depressed, a logic 0 appears at the respective input and, as discussed earlier,
the output of
the gate immediately swings to logic 1. The output continues to be in that
condition as long as the bell-push switch is held depressed.
The
output of this gate is used to activate a relay via transistor Tl. The
normally-open contacts of the relay are connected to an electric bell. So,
whenever any of the bell switches is pushed, the bell rings.
The
complementary outputs of the flip-flops are connected to quad-input nand gate
IC3(b). Since complementary outputs of the flip-flop are normally held at
logic 1 (the reset state of the flip-flop), the output of this gate is at logic
0. However, if any of the flip-flops gets a set pulse, i.e. if logic 0 appears
at the set inputs, the Q inverse output of the flip-flop goes to logic 0, and
consequently the output of the quad input nand gate IC3(b) goes to logic 1.
The
output of IC3(b) gate is fed to pin
numbers 4 of IC4 and IC5. IC4, a 555 timer, is wired in the astable mode. The
values of R11, R12 and C1 are so chosen that the mark and space periods are
about five seconds and one second respectively. When the output of IC3(b) goes
to logic 1, IC4 is enabled and the output at its pin 3 goes high for five
seconds and low for the next one second, and so on.
The
output of IC4 is fed to npn transistor SL100, which saturates whenever the
output goes high and discharges capacitor C3. As such, IC5, which is also wired
as an astable multivibrator, can be disabled from two sources. First, it
remains disabled as long as pin 4 is held low or second, whenever the output at
pin 3 of IC4 goes high.
The
output of IC5 is fed to a speaker via current limiting resistor R16. It must be
noted that the maximum current that a 555 IC can safely source is around 200mA.
The combined impedance of the speaker and series resistance should therefore be
around 60-ohm.
Reverting to the flip-flops, it will be
observed from Figure 1that the Q outputs of the flip-flops are
connected to light emitting diodes Dl, D2, D3 and D4 via current limiting
resistors. Since, normally (i.e. in the reset state), the Q output of the
flip-flop is at logic 0, the LEDs will remain unlighted. But immediately after
receipt of a negative pulse at the set input, the Q output will go to logic 1
and the respective LED will light up. The LED will thus provide a visual
indication of the calling station.
Thus,
whenever any bell-push switch is depressed, the main bell will ring (only as
long as the switch is held depressed), the corresponding LED will light up, and
to remind the office boy short beeps will sound till he calls up to attend to
the executive’s need and depresses the master reset switch.
In the circuit shown only
one master reset switch has been provided. However, if desired, a separate
reset switch for each station can also be provided by using three-input nand
gates instead of the two-input nand gates in the flip-flops. These reset
switches may be mounted at the entrance of each cabin. Further, if desired, the
LEDs can be replaced by small bulbs if suitable transistors capable of carrying
the required current are connected to the Q outputs of the flip-flops.
Fig 2 shows the circuit of
a power supply which may be used. A voltage regulator IC has been used to
simplify construction of the power supply.
'Priority' system
The
above system works very well as long as the office boy has to attend to
executives of nearly the same rank, or is intelligent enough
to discriminate as to which executive should be attended to first in case more
than one bell switch has been depressed at the same time. The circuit shown in
Fig. 3 can discriminate according to the seniority of the executive. The chief
executive has been provided with two bell switches, both having the same
priority. One bell may be used by him to call the office boy, and the other may
indicate a repetitive chore like ordering tea for the guests etc.
The
circuit uses a 10-line to 4-line priority encoder IC 74147. Only four inputs of
the IC have been used, so that four mutually exclusive outputs are obtained.
The bell switches Sa and Sb
have the topmost priority, and LEDs D1 and D2 will light up in preference to
all the other LEDs. Similarly, LED D3 shall have preference over LEDs D4 and
D5, and so on.
Thus,
if bell-push switch Sa, Sc and Sf
are depressed simultaneously, only LED D1 will light up. After attending
executive A, the office boy would press the reset switch Ra.
Since executives C and E have not yet been attended, LED D3 will now light up.
After attending D3, he will be called upon to attend executive D5. In this
manner, the office boy shall be clearly instructed as to which executive he
should attend to at any one time.
A
PCB layout for the Priority Office Call Bell is shown below.
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